1. Field of the Invention
The present invention relates to semiconductor integrated circuit memories. More particularly, the present invention relates to a method and circuit for generating sequences of address bits to facilitate burst access of a synchronous memory.
2. Description of the Prior Art
FIG. 1 is a schematic diagram of a conventional burst address counter 100 for a synchronous memory 101. Burst address counter 100 provides a sequence of burst address signals A' 14:0! which point to contiguous memory storage locations within memory 101, such that the data values (e.g., DATAM:N!) stored at these locations are readily accessible to the system data bus 102.
Burst address counter 100 includes binary counter 110, address register 111, AND gates 112 and 113, exclusive NOR gates 114 and 115, and inverters 116-117. Binary counter 110 includes registers 121 and 122, inverter 123 and exclusive OR gate 124. Burst counter 100 operates as follows. Prior to a burst access, the initialization signal (INIT), which is applied to an input terminal of AND gate 112, and the advance signal (ADV), which is applied to an input terminal of AND gate 113, are both in logic low states. As a result, the clock signal (CLK), which is applied to input terminals of both AND gate 112 and AND gate 113, has no effect on the output signals provided by AND gates 112 and 113. To initiate a burst access, the INIT signal is asserted high. When the CLK signal next transitions to a logic high state, AND gate 112 provides a logic high CLEAR signal to the clock input terminal of address register 111 and to the clear input terminals of registers 121 and 122. This logic high CLEAR signal causes an initial address signal A14:0! to be latched into address register 111. This initial address signal A14:0! remains latched in register 111 until the next rising edge of the CLEAR signal. The logic high CLEAR signal also clears the contents of registers 121 and 122, thereby initializing the Q0 and Q1 output signals provided by registers 121 and 122, respectively, to logic low values (i.e, Q1, Q0=0,0).
The logic low Q0 and Q1 output signals are applied to input terminals of exclusive NOR gates 114 and 115, respectively. The two least significant address bits, A0! and A1!, are also applied to input terminals of exclusive NOR gates 114 and 115, respectively. The output signals provided by exclusive NOR gates 114 and 115 are routed through inverters 116 and 117, respectively, to provide burst address signals A'0! and A'1!, respectively. The logic low values of the Q0 and Q1 output signals cause the burst address signals A'0! and A'1! to be initially equal to input address signals A0! and A1!, respectively. The burst address signals A'1! and A'0! are concatenated with initial address bits A14:2! to form burst address A'14:0!.
The INIT signal is subsequently de-asserted low, thereby causing the CLEAR signal to transition to a logic low state. The ADV signal is then asserted high, thereby enabling the CLK signal to be transmitted through AND gate 113. The CLK signal is applied to the clock input terminals of registers 121 and 122. On successive rising edges of the CLK signal, the Q1, Q0 output signals transition from their initial values of 0,0 to 0,1 to 1,0 to 1,1. As a result, the burst address signals A'1! and A'0! transition from their initial values of A1! , A0! to A1! , A0! to A1!, A0! to A1! , A0! . Address signals A14:2! remain constant during this time. Consequently, the burst address signals A'14:0! are automatically incremented in a predetermined sequence in response to the CLK signal. Burst counter 100 can operate in an interleaved or linear mode, and may count up or down, depending upon the initial address and operational mode.
The logic circuitry within burst address counter 100 introduces delay in providing the burst address signal A'14:0! to memory 101. Important delay parameters in synchronous memories include the address set-up time, the address hold time, and the time required for valid data to be provided by the memory after the initial transition of the clock signal. The address set-up time is defined as the amount of time that the address must be valid before a transition of the clock signal (e.g., a low to high transition) activates the burst counter 100 to load the initial address. The address hold time is defined as the time that the address must be present after the clock transition so as to insure the capture of the value address by the burst counter 100.
There are three and a half logic gate delays which exist between the transition of the CLK signal and the generation of burst address signal A'14:0! in burst address counter 100. A logic gate delay is defined as the time required for a signal to pass through a logic device. Binary counter 110 introduces one logic gate delay, exclusive NOR gates 114 and 115 introduce 1.5 logic gate delays and inverters 116 and 117 introduce one logic gate delay. FIG. 2 is a schematic diagram of exclusive NOR gate 114 and inverter 116. Exclusive NOR gate 114 includes two inverters 201 and 202, which introduce one logic gate delay, and transmission gates 203 and 204, which introduce one-half logic gate delay. Inverter 116 introduces one logic gate delay.
FIG. 3 is a timing diagram illustrating the 3.5 logic gate delays between the rising edge of the CLK signal and generation of burst address signal A'14:0!. This logic gate delay is included in the address set-up time, the address hold time, and the time required for valid data to be provided by the memory after the initial transition of the clock signal. It would therefore be desirable to reduce the logic gate delay between the rising edge of the clock signal and the generation of the burst address signal A'14:0!.